Semiconductor devices, and in particular semiconductor memory devices such as DRAM memory modules, are generally provided with redundant word or bit lines. This redundancy ensures operation even if, for example, in the complex process for fabricating the delicate structures, one word or bit line is interrupted or short-circuited with another. These faults are detected in a wafer test and corrected at the wafer level, if possible by incorporating redundant word or bit lines. The redundant lines are linked via fuses which are blown by means of a laser beam pulse having a predetermined energy content. This pulse, in accordance with the wafer test, forwards a predetermined potential preferably to a downstream latch device or not to forward it in the blown state.
The increased integration density and the use of the double data rate (DDR) scheme in DRAM memories requires more redundancies and therefore, more fuses are required for linking them. However, the fuses that are to be blown in a manner dependent on the wafer test result cannot be arranged arbitrarily close together. This arrangement is important because on the one hand, the laser for blowing the fuses cannot be adjusted with arbitrary precision and, on the other hand, the laser energy pulse must be sufficient to melt the conductive material of the fuse without, the adjacent fuse likewise being blown at the same time in an undesirable manner. The fuses must also be arranged in a manner to avoid residues of the melted fuse which might in turn produce a short circuit. Furthermore, a complex arrangement of the fuses is not desirable since the blowing of the fuses by means of the laser must be able to be carried out in a short time (i.e. efficiently). Hitherto the laser device has not been able to adjusted with arbitrary two-dimensional precision and rapidity with regard to the wafer.
FIG. 4 illustrates a customary semiconductor device with a known fuse layout in plan view. A first patterned, conductive interconnect plane 11, which forms interconnects in the region of the fuse device, is provided on a passivated semiconductor substrate 10. Situated above said plane 11 is a second patterned, conductive interconnect plane 13, which is isolated from the first patterned, conductive interconnect plane 11 by a passivation 12 and likewise forms interconnects. A third patterned, conductive interconnect plane 15, which is arranged above the second patterned, conductive interconnect plane 13 and is likewise spaced apart from the second patterned, conductive interconnect plane 13 by a passivation 14. Fuse regions 17 are provided in two rows. In order to be able to blow this upper patterned conductive interconnect plane 15 or the fuse region 17 of this interconnect plane by means of the laser, it must be directly accessible from above. Therefore, in the passivation layer 16 applied on the wafer, windows 24 are provided above the fuse devices, in which no passivation 16 is provided.
Via contact devices 19, 20, the interconnects of the third patterned, conductive interconnect plane 15 are selectively connected either to the first patterned, conductive interconnect plane 11 or the second patterned, conductive interconnect plane 13. These contacts are made so that, in the known layout three fuses 17 are in each case accessible via three interconnect planes 11, 13, 15 in the plane of the drawing and can be contact-connected via the terminal region thereof (on the right-hand side) according to layout of FIG. 4.
On the left-hand side, all the conductive planes 11, 13, 15 are provided with a predetermined potential which is or is not connected to the terminals on the right-hand side depending on whether or not a fuse is blown in the fuse region 17. Whilst complying with the required distance 18 (fuse pitch) between the adjacent fuses 17 of this conventional left/right “trident” fuse arrangement, there are only a small number of fuses available per area. Furthermore, the contact devices between the various electrically conductive, patterned interconnect planes 11, 13, 15 are exposed, particularly in the accelerated stress test, to an increased corrosion resulting in failures of the contact devices. This type of failure is referred to as “HAST fails”.